Voltage-controlled oscillators (VCOs) are commonly used in phase-locked loops (PLLs) to perform the function of frequency synthesis. FIG. 1 illustrates a block diagram of a known PLL 1 that is configured to perform frequency synthesis. The PLL 1 is a negative feedback control system that maintains a known phase and frequency relationship between the output clock 3 of the VCO 2 and the input reference clock (REFCLK) 4. The phase comparator 5 compares the phase of the output clock 3 with the phase of the input reference clock 4 to produce a phase error signal corresponding to the difference between the phase of the output clock 3 and the phase of the input reference clock 4. In cases where the PLL 1 includes a frequency divider 7 for performing multiplication of the input reference clock frequency, the output clock 3 is divided by some frequency divider value to convert the output clock signal into a feedback signal having a frequency that substantially matches the frequency of the input reference clock 4. The loop filter 6 processes the phase error signal output from the phase comparator 5 and produces a control voltage signal accordingly to steer VCO 2 over the frequency tuning range of the VCO 2 in order to maintain phase lock with the reference clock 4. The loop filter 6 characteristics are designed to achieve PLL 1 dynamic responses that are tailored for the intended PLL application.
In the example shown in FIG. 1, fvco=NPLL×fREFCLK, where fvco is the frequency of the output clock 3 of the PLL 1, NPLL is the frequency divider value of the frequency divider 7 and fREFCLK is the frequency of the input reference clock 4. For fixed frequency operation, some frequency tunability range is normally incorporated into the VCO 2 since the output clock 3 frequency of the VCO 2 has inherent sensitivities to the operating supply voltage (VDD) and to temperature, as well as to statistical variations in circuit manufacturing. In many PLL implementations, it is desirable that the VCO spans a wider range of output frequencies given the same range of VCO control voltage input. Advantages include cost and power savings gained from employing simpler system architectures for multi-frequency applications. However, incorporating such a large tuning range increases the susceptibility of the VCO to noise injected additively at the control voltage node, which often renders such PLLs inadequate for implementations that require extremely low jitter performance. In other words, a given voltage noise level generates significantly greater frequency modulation at the output of a VCO with a significantly larger tuning range compared to the amount of frequency modulation generated by the same voltage noise level at the output of a VCO with a smaller tuning range.
Fortunately, the entire frequency tuning range is not continuously required in all PLL implementations. For example, in high-speed serial data communications, once a data rate or frequency is selected, the PLL operates at this frequency uninterrupted until another data rate is selected. In such instances, PLLs with calibrated VCOs prove useful. FIG. 2 illustrates a block diagram of a PLL 10 that includes a calibrated VCO 12. The PLL 10 shown in FIG. 2 operates in essentially the same manner in which the PLL 1 shown in FIG. 1 operates, except that the VCO 12 shown in FIG. 2 is a calibrated VCO whereas the VCO 2 shown in FIG. 1 is not a calibrated VCO. The components 15, 16 and 17 shown in FIG. 2 are identical to components 5, 6 and 7, respectively, shown in FIG. 1.
Calibrated VCOs of the type shown in FIG. 2 utilize two sets of frequency-tuning elements that are driven by independent sets of control voltages, as described below with reference to FIG. 3. During the calibration sequence, the coarse frequency control signal or signals is determined based on the selected input REFCLK clock frequency. Following calibration, normal PLL operation ensues with the fine frequency control signal output from the loop filter 16 adjusting the VCO input to compensate for VCO sensitivities to VDD and temperature drifts from the calibration condition.
FIG. 3 illustrates a block diagram of an implementation example of the calibrated VCO 12 shown in FIG. 2. The calibrated VCO 12 has a pair of ideally identical inductors 21 and 22, variable capacitors 23 and 24, and cross-coupled gain transistors 25 and 26. Each resonant tank 27 and 28 oscillates differentially with respect to the other tank at a frequency, f=½π(LC)0.5, where L is the value of the inductance of the tank inductor and C is the value of the total capacitance of the tank. The cross-coupled gain transistors 25 and 26 periodically inject energy into the tanks 27 and 28 to sustain oscillations that would otherwise decay and disappear due to parasitic resistive losses in the inductors and capacitors.
Employing a calibrated VCO provides better jitter performance as long as the coarse frequency tuning elements have less susceptibility to control voltage noise in comparison to the fine frequency tuning elements. The VCO 12 shown in FIG. 3 is a resonant inductor-capacitor (LC)-based VCO that employs an array of inversion-mode MOSFET varactors 23 and 24 that function as nonlinear voltage-controlled capacitors to tune the VCO. Each of the varactors 23 and 24 receives a control voltage that is independently controlled, though varactors 23 are typically controlled by a set of control voltages. The VCO 12 has M and N varactors 23 and 24, respectively, (where M and N are integers) for coarse and fine frequency tuning, respectively. The VCO output frequency is given by:
                              f          vco                ≈                ⁢                  1                      2            ⁢                          π              /                                                LC                  total                                                                                            =                ⁢                  1                      2            ⁢            π            ⁢                                          L                ·                                  (                                                            C                      o                                        +                                                                  ∑                                                  k                          =                          1                                                M                                            ⁢                                              C                                                  coarse                          ,                          k                                                                                      +                                          NC                      fine                                                        )                                                                        where
C0=fixed capacitance in the tank due to the cross-coupled transistors and parasitics,
Ccoarse,k=capacitance contribution of the kth coarse frequency tuning varactor, and
Cfine=capacitance contribution of each fine frequency tuning varactor.
FIG. 4 illustrates a plot 30 of gate capacitance versus control voltage that demonstrates the capacitance-voltage (C-V) characteristics for an n-channel inversion-mode MOSFET varactor of the type used in the VCO 12 shown in FIG. 3. The control voltage for the fine frequency tuning varactors 24 would nominally be positioned somewhere along the depletion-to-inversion transition 31 (highly sloped region of C-V characteristic plot 30). On the other hand, control voltages for the coarse frequency tuning varactors 23 would be driven to either GND or VDD, depending on the required calibration setting, such that the coarse frequency may be modulated by a total capacitance of MΔC across the coarse tuning range of the VCO. The flatness of the capacitance vs. voltage (C-V) characteristic at control voltages of GND and VDD translates to minimal jitter or associated frequency modulation induced by noise added to the coarse control voltage line.
Calibrated VCOs require some sort of calibration algorithm state machine that determines the coarse calibration setting, CS, for the corresponding M coarse frequency tuning varactor control voltages for a given input reference frequency (fREFCLK). In the example shown, such a state machine would determine how many of the M varactors 23 are driven to VDD and how many are driven to GND. In a numerical illustration, if it is assumed that CS=15 is required to calibrate closely to some reference frequency, e.g., 125 MegaHertz (MHz), then 15 coarse varactor control voltages are driven to VDD and (M-15) coarse varactor control voltages are driven to GND. The calibration algorithm is also responsible for effectively driving the fine frequency tuning varactors 24 to their average value, which is commonly referred to as “midrailing” the capacitors, during calibration. This ensures that immediately after calibration, the PLL has approximately equal bidirectional tuning range of approximately ±½ NΔC.
As previously mentioned, fine frequency tuning enables the PLL to compensate for VCO frequency sensitivities to allowable VDD and temperature drifts following calibration. Incorporating excessive fine frequency tuning range is not prudent as it compromises jitter performance. Consequently, an optimized VCO design should have just enough fine frequency tuning to compensate for such sensitivities but not so much tuning so as to introduce substantial jitter. Furthermore, it is imperative that these sensitivities be measured in order to confirm that sufficient fine frequency tuning is available when the PLL is operating in the field.
One technique that is currently used for measuring such sensitivities is known as the direct measurement approach. The direct measurement approach involves calibrating the oscillator at some input frequency, supply voltage (VDD) and temperature condition, and then measuring the PLL output jitter at other supply voltage and temperature conditions. If the VCO is forced to operate beyond its fine frequency tuning limits, the PLL will be unable to compensate for the VCO sensitivities and will generate excessive output jitter as a result. In essence, if the VCO is forced to operate beyond its fine frequency tuning capabilities, then the PLL that employs the VCO will fail to maintain frequency and phase lock.
The calibration algorithm uses counters and other logic to determine, at each input reference clock frequency, which calibration setting produces a clock frequency at the output of the feedback frequency divider circuit that most closely matches the input reference clock frequency. With reference again to FIG. 2, during calibration, the phase comparator 15 is disabled and the fine tuning control voltage output from the loop filter 16 is “midrailed”. A first counter 13 receives the input reference clock signal and a second counter 14 receives the clock frequency output from the feedback frequency divider 17. The counters 13 and 14 increment on the rising edges of the clock frequency signals. The counter values are output to a subtractor 18 that subtracts the value of counter 14 from the value of counter 13.
In one example of a calibration algorithm, the coarse tuning calibration setting (“coarse control voltage(s)”) input to the VCO 12 is sequentially swept from its minimum calibration setting to its maximum calibration setting. At each setting, both counters 13 and 14 are initially reset, after which they will begin to increment at a rate proportional to the input reference clock and feedback clock frequencies. At the beginning of the calibration process, the value in the counter 13 will be greater than the value in the counter 14, and therefore the sign of the result of the subtraction will be positive. However, as the calibration setting is increased, at some point in time, the clock frequency output from the frequency divider will exceed the input reference clock frequency. At that point in time, the sign of the result of the subtraction will change from positive to negative. The calibration algorithm will then compare the magnitude of the result of the subtraction just before the change in sign with the magnitude of the result that caused the sign change. The coarse calibration setting associated with the smallest difference in magnitude will then be saved in memory as the calibration setting that corresponds to the associated input reference clock frequency and associated VCO output clock frequency (the VCO output clock frequency is equal to the input reference clock frequency times the frequency divider value).
Once the calibration settings have been determined for each input reference clock frequency, the VCO output clock jitter at each input frequency and at each possible permutation of supply voltage and temperature conditions must be measured and a determination must be made as to whether the PLL was unable to maintain lock due to the inability of the VCO to provide the necessary fine tuning.
This direct measurement approach has several important drawbacks. One drawback is that jitter measurements are difficult and tedious to obtain and can often be inaccurate. Obtaining the measurements is an extremely time consuming and cumbersome task because the measurements need to be repeated across many input reference clock frequencies, across all possible permutations of calibration conditions (i.e., VDD and temperature), and across possible permutations of VDD and temperature drifts from the calibration condition, and determinations must be made at each input reference clock frequency and set of conditions as to whether jitter in the VCO output clock indicates that the PLL is unable to maintain lock.
Accordingly, a need exists for a method and apparatus for easily and quickly making a determination as to whether the VCO has sufficient fine frequency tuning range over the range of input reference clock frequencies and over different permutations of supply voltage and temperature.